This invention relates generally to digital electronic counting techniques, and, more specifically, to an incrementer/decrementer circuit.
There are many instances in digital computer design where a counter is provided for counting up (incrementing) one binary number at a time and/or counting down (decrementing) one binary number at a time. One widespread use of such an incrementer/decrementer is for accessing a computer memory by stepping through a number of sequential memory addresses, one at a time. The memory address usually contains a number of bits equal to the width of the computer system address bus, typically 8, 16, 32, 64 or more bits, depending upon the particular application and size of the computer system.
This is done, for example, in a microcomputer direct memory access (DMA) integrated circuit chip. An incrementer/decrementer circuit in a DMA is provided with a beginning address by the computer system microprocessor and an instruction as to whether the memory is to be accessed in an address space above (increment) or below (decrement) this beginning address. The DMA incrementer/decrementer then puts the beginning address out onto the computer system address bus and increments or decrements that address by one binary count at a time. Thus, all addresses within the designated address space are accessed in sequence for reading or writing data into those memory locations.
Such an incrementer/decrementer circuit is essentially a counter that adds or subtracts a binary one to the current address in order to obtain a new address. An exclusive OR (XOR) gate is typically provided for each bit of the address word and receives as an input the current value of its associated address bit and a carry-in from the addition operation of the lesser significant bit adjacent the current bit. The carry-in bit values are typically provided by a carry chain that has a circuit stage for each bit of the address. The carry chain stages are connected in series and each typically consists of a single AND gate whose inputs are the carry-in signal from the previous stage and the current value of the address bit with which the stage is associated. A carry bit is thus advanced through the chain from its initial stage associated with the least significant address bit through the stage associated with the most significant bit of the address. Some time is of course required for each carry bit to progress through the chain and thus places some limitation on the speed of such an incrementer/decrementer. However, a carry chain is preferred over other incrementer/decrementer logic configurations which usually requires a much larger number of logic gates and thus consumes more space on an integrated circuit chip.
An important and popular technology for constructing such logic gates is with the use of complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs). CMOS technology does not permit implementation of an AND logic function in a single gate so it is commonly accomplished by a series combination of a NAND gate and an inverter. Thus, a carry chain can be provided as part of an incrementer/decrementer with each stage including two such gates. The increased number of gates, of course, increases the minimum amount of time that is necessary for a carry bit to progress completely along the chain, since there is a potential delay imposed by each gate. This can be a limitation on the operating speed of the circuit, and then of the complete computer system when utilizing the circuit, especially when the address is 16, 32 or more bits wide since this requires, respectively, 32 or 64 gates in the carry chain.
Therefore, it is a primary object of the present invention to provide an incrementer/decrementer technique having a carry function that operates with increased speed, minimizes the amount of integrated circuit area necessary for its implementation, and which is easy to design and fabricate.
It is a more specific object of the present invention to provide such a technique in circuits implemented in CMOS technology.